In this thesis, sequential logic circuits have been implemented using spatial wavefunction-switched field-effect transistor (SWSFET). The spatial wavefunction-switched field-effect transistor (SWSFET) is one of the promising quantum well devices that transfers electrons from one quantum well channel to the other channel based on the applied gate voltage. This eliminates the use of more transistors as we have coupled channels in the same device operating at different threshold voltages. This feature can be exploited in many digital integrated circuits thus reducing the count of transistors which translates to less die area. The simulations of basic sequential circuits like SR latch, D latch are presented here using SWSFET based binary logic gates. The circuit model of a SWSFET was developed using Berkeley short channel IGFET model (BSIM3) in Cadence simulator. Multi-valued logic is an interesting aspect of SWSFET as it is capable of having multiple channels. Since each channel has a threshold voltage and can be selected by applying the appropriate gate voltage, SWSFET offers several design possibilities with more than just two states. In this thesis, a quaternary D flip flop is presented with simulations done using VHDL Behavioral model. The number of transistors is reduced by nearly 80% when compared to the conventional CMOS circuits. By using quaternary to binary and binary to quaternary conversion circuits, it is possible to integrate the quaternary circuits with the existing binary circuits.
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